1. Field of the Invention
This invention relates to devices methods for fabricating integrated circuits and more particularly to a method for fabricating a ferroelectric capacitor in an integrated circuit (IC) device, as well as the ferroelectric capacitor structure and the IC device comprising same.
2. Description of the Related Art
Integrated circuit chips include a substrate of semiconductive material with component structures of electronic circuits, e.g., transistors and resistors, fabricated within the substrate structure. Additional electrical devices and precursor and/or component structures of the electronic circuits are fabricated over the top of the substrate. These additional devices and structures of circuits include conductive leads, capacitors, and parts of transistors. The devices fabricated above the substrate typically require many layers, of a variety of materials, e.g., conductors, semiconductors, insulators, and barriers.
Conductive layers in integrated circuit devices often are fabricated in aluminum (Al), copper (Cu) or tungsten (W). Each conductive layer is deposited over an underlying surface and typically is patterned and etched into a shape that is predetermined by designers to perform a desired function in the final circuit product. Typical integrated circuit devices require multiple layers of conductive materials. Undesirable electrical shorting between conductive layers is prevented by interposing one or more layers of insulative material between each conductive layer and the next conductive layer above and/or below it.
Fabrication of an integrated circuit capacitor requires the fabrication of two layers of conductive materials forming the conductive plates of the capacitor. Those two plates are separated by a layer of dielectric material. During recent years researchers and designers have been investigating the use of high dielectric constant materials for use as integrated circuit capacitor dielectrics. Some promising high dielectric constant materials include lead zirconium titanate (PbZrTiO.sub.3), sometimes hereinafter denoted "PZT," and strontium bismuth tantalum oxide (SrBi.sub.2 Ta.sub.2 O.sub.9), sometimes hereinafter denoted "SBT." Because of the hysteresis type voltage-current (VI) characteristics of these materials, they are known as ferroelectric materials.
During fabrication of integrated circuit devices including capacitors with a ferroelectric dielectric material, the ferroelectric material is deposited before the second, or upper, plate of the capacitor is deposited and formed. After the upper plate is formed, a layer of insulative material typically is deposited to insulate the upper plate from another layer of conductive material, generally referred to as a metal layer. The process of shaping the upper plate of the capacitor can expose a portion of the ferroelectric material before the insulative material is to be deposited.
A standard insulative material, long used in fabrication of integrated circuit devices, is silicon dioxide (SiO.sub.2). Because developers have lengthy experience working with silicon dioxide and appropriate equipment for depositing it, silicon dioxide is the insulative material of choice for the layer of intermetal insulator between the upper capacitor plate and the next overlying conductive layer.
Silicon dioxide appears to be a very good choice as the intermetal layer material except that in combination with the ferroelectric material, it creates problems while it is being deposited or during subsequent processing steps. A primary problem is that silicon dioxide reacts directly with the exposed parts of PbZrTiO.sub.3 or SrBi.sub.2 Ta.sub.2 O.sub.9 while the silicon dioxide is being deposited or during the subsequent processing steps. This reaction degrades the electrical properties of the ferroelectric material. Chemical vapor deposition (CVD) is a process used for depositing the silicon dioxide. The CVD process uses either hydrogen or silicon hydride (SiH.sub.4), as a carrier gas. Both of these carrier gas species are reducing gases. These reducing gases can react directly with the ferromaterial to form water which in turn reacts with the ferroelectric material and degrades its electrical properties.
Additionally, the deposited layer of silicon dioxide has a residual compressive stress in its crystalline structure. This compressive stress is translated into the ferroelectric material and degrades the electrical properties of the ferroelectric material.
Developers are left with a dilemma of finding a different material than silicon dioxide for use as an intermetal insulator or of finding a new device structure and a new method for depositing silicon dioxide without degrading the desirable electrical characteristics of the ferroelectric material, used as a capacitor dielectric.